1. Field of the Invention
The present invention relates to Bi-CMOS logic gate circuits for low-voltage, fine-structured semiconductor integrated circuits.
2. Description of the Related Art
FIG. 1 shows an inverter circuit consisting of a conventional Bi-CMOS logic gate circuit. The structure of the circuit is based on the "Novel Bi-CMOS Circuit Using Merged Devices Structure" at The 1989 SPRING NATIONAL CONVENTION RECORD, THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS C-274.
In FIG. 1, the input terminal IN is connected to each gate of the p-channel MOS transistor M1 and the n-channel MOS transistor M2. The source of the transistor M1 is connected to the supply voltage V.sub.DD, while the source of the transistor M2 is connected to the ground voltage V.sub.SS. Connected across the source and drain of the transistor M1 is the collector-base path of the n-p-n transistor Q1, whereas connected across the source and drain of the transistor M2 is the collector-base path of the p-n-p transistor Q2. Two diodes D1 and D2 are connected in series across the node A, to which both transistor M1's drain and transistor Q1's base are connected, and the node B, to which both transistor M2's drain and transistor Q2's base are connected. These diodes D1 and D2 are used to store and retain the charge in the diffusion capacitance between the base and emitter of the bipolar transistors. The use of the diodes D1 and D2 enables high speed operation even with low loads.
Each emitter of the transistors Q1 and Q2 is connected to the output terminal OUT, which forms a complementary Bi-CMOS logic gate circuit made up of the n-p-n transistor Q1 and the p-n-p transistor Q2 at the output stage.
The operation of the aforementioned Bi-CMOS logic gate circuit will now be explained. Suppose that the output OUT is kept at the "H" (High) level, or at the value equal to the supply voltage V.sub.DD minus the base-emitter voltage V.sub.BE of the transistor Q1 (Q2).
When the input terminal IN is at the "H" level, the n-channel MOS transistor M2 conducts and the p-channel MOS transistor Ml is cut off, causing the voltage of the node B to be nearly the ground voltage V.sub.SS (OV). This makes the transistor Q2 conduct, causing the voltage of the output terminal OUT to be the voltage V.sub.BE (nearly 0.7 V) across the base and emitter of the transistor Q2.
When the input terminal IN changes to the "L" (Low) level, then the p-channel MOS transistor M1 conducts and the N-channel MOS transistor M2 is cut off, causing the voltage of the node A to be the supply voltage V.sub.DD. This makes the transistor Q1 conduct, causing the voltage of the output terminal OUT to be (V.sub.DD -V.sub.BE).
Such Bi-CMOS logic gate circuits have grown smaller, which results in narrower gate widths of the elements, lowering the breakdown voltages of the elements. The decreased withstand voltages for the elements require low-voltage operation. Suppose, for example, that in a 0.5 .mu.m rule fine Bi-CMOS circuit designed not to lose the high-speed feature, V.sub.DD is lower than 5 V, e.g., 3.3 V. When V.sub.DD =3.3 V, however, the "L" level of the output is V.sub.SS =0.7 V and the "H" level is 2.6 V, equivalent to V.sub.DD (3.3 V)-V.sub.BE (0.7 V). This offers an output amplitude of 1.9 V, reducing heavily the noise margin of the circuit compared with the CMOS logic gate.